Current consumption 13 µA typ.
Available watchdog timeout periods are
3.4 ms, 6.3 ms, 102 ms, and 1.6 s
Chip enable input
Open drain or push-pull WDO output
Operating temperature range: –40 to 125 °C
Packages: SOT23-5 and SC70-5
HBM: 2000 V
CDM: 1000 V
UPS (uninterruptible power supply)
The STWD100 watchdog timer circuits are self
contained devices which prevent system failures
that are caused by certain types of hardware
errors (such as, non-responding peripherals and
bus contention) or software errors (such as a bad
code jump and a code stuck in loop).
The STWD100 watchdog timer has an input,
WDI, and an output, WDO . The input is used to
clear the internal watchdog timer periodically
within the specified timeout period, twd. While the
system is operating correctly, it periodically
toggles the watchdog input, WDI. If the system
fails, the watchdog timer is not reset, a system
alert is generated and the watchdog output,
WDO , is asserted.
The STWD100 circuit also has an enable pin,
EN , which can enable or disable the watchdog
functionality. The EN pin is connected to the
internal pull-down resistor. The device is enabled
if the EN pin is left floating.